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Verification vs. Validation

Printed From: One Stop Testing
Category: Software Testing @ OneStopTesting
Forum Name: Bug Report @ OneStopTesting
Forum Discription: After Creating the Test Plan, Writing the Test Cases and using them, Finally We need to generate those Bug Reports which Proves that Testers are Good enough & most importantly Indispensable.
URL: http://forum.onestoptesting.com/forum_posts.asp?TID=699
Printed Date: 16Nov2024 at 7:32pm


Topic: Verification vs. Validation
Posted By: Rupali
Subject: Verification vs. Validation
Date Posted: 05Apr2007 at 3:52am

Testing is a process of reducing risk by comparing "what is" against "what should be".

Software verification is often confused with software validation. The difference between 'verification and validation:

Difference http://en.wikipedia.org/wiki/Verification - Verification http://en.wikipedia.org/wiki/Validation - Validation
Asks: "Are we building the product right?"
Does the software conform to its specification?
"Are we building the right product?"
Is the software doing what the user really need/want?
Focus: verifies that the final product satisfies or matches the validates that the product design satisfies the
Basis: original design (from low-level engineering). intended usage (from high-level marketing).
Conclusion from http://en.wikipedia.org/wiki/Verification_and_Validation - Capability Maturity Model (CMMI-SW v1.1) the work products properly reflect the requirements specified for them. the product, as provided, will fulfill its intended use.
The aim of testing: Find errors introduced by an activity, i.e. check if the product of the activity is as correct as it was at the beginning of the activity. Declare whether the product of an activity is indeed what is expected, i.e. the activity extended the product successfully.

In the electronics industry:

    Near the end of the Prototyping stage, after engineers create actual working samples of the product they plan to produce, Engineering Verification Testing (EVT) uses prototypes to verify that the design meets pre-determined specifications and design goals. This is done to validate the design as is, or identify areas that need to be modified.

    After prototyping, and after the product goes though the Design Refinement cycle when engineers revise and improve the design to meet performance and design requirements and specifications, objective, comprehensive Design Verification Testing (DVT) is performed to verify all product specifications, interface standards, OEM requirements, and diagnostic commands.

    Process (or Pilot) Verification Test (PVT) is a subset of Design Verification Tests (DVT) performed on pre-production or production units to Verify that the design has been correctly implemented into production.




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