Active TopicsActive Topics  Display List of Forum MembersMemberlist  CalendarCalendar  Search The ForumSearch  HelpHelp
  RegisterRegister  LoginLogin


 One Stop Testing ForumSoftware Testing @ OneStopTestingBug Report @ OneStopTesting

Message Icon Topic: Verification vs. Validation

Post Reply Post New Topic
Author Message
Rupali
Groupie
Groupie
Avatar

Joined: 05Apr2007
Online Status: Offline
Posts: 43
Quote Rupali Replybullet Topic: Verification vs. Validation
    Posted: 05Apr2007 at 3:52am

Testing is a process of reducing risk by comparing "what is" against "what should be".

Software verification is often confused with software validation. The difference between 'verification and validation:

Difference Verification Validation
Asks: "Are we building the product right?"
Does the software conform to its specification?
"Are we building the right product?"
Is the software doing what the user really need/want?
Focus: verifies that the final product satisfies or matches the validates that the product design satisfies the
Basis: original design (from low-level engineering). intended usage (from high-level marketing).
Conclusion from Capability Maturity Model (CMMI-SW v1.1) the work products properly reflect the requirements specified for them. the product, as provided, will fulfill its intended use.
The aim of testing: Find errors introduced by an activity, i.e. check if the product of the activity is as correct as it was at the beginning of the activity. Declare whether the product of an activity is indeed what is expected, i.e. the activity extended the product successfully.

In the electronics industry:

    Near the end of the Prototyping stage, after engineers create actual working samples of the product they plan to produce, Engineering Verification Testing (EVT) uses prototypes to verify that the design meets pre-determined specifications and design goals. This is done to validate the design as is, or identify areas that need to be modified.

    After prototyping, and after the product goes though the Design Refinement cycle when engineers revise and improve the design to meet performance and design requirements and specifications, objective, comprehensive Design Verification Testing (DVT) is performed to verify all product specifications, interface standards, OEM requirements, and diagnostic commands.

    Process (or Pilot) Verification Test (PVT) is a subset of Design Verification Tests (DVT) performed on pre-production or production units to Verify that the design has been correctly implemented into production.



Edited by moderator - 26Apr2007 at 11:56pm



Post Resume: Click here to Upload your Resume & Apply for Jobs

IP IP Logged
Post Reply Post New Topic
Printable version Printable version

Forum Jump
You cannot post new topics in this forum
You cannot reply to topics in this forum
You cannot delete your posts in this forum
You cannot edit your posts in this forum
You cannot create polls in this forum
You cannot vote in polls in this forum



This page was generated in 0.969 seconds.
Vyom is an ISO 9001:2000 Certified Organization

© Vyom Technosoft Pvt. Ltd. All Rights Reserved.

Privacy Policy | Terms and Conditions
Job Interview Questions | Placement Papers | Free SMS | Freshers Jobs | MBA Forum | Learn SAP | Web Hosting